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dc.contributor.authorLiu, L-
dc.contributor.authorChen, N-
dc.contributor.authorMeng, H-
dc.contributor.authorZhang, L-
dc.contributor.authorWang, Z-
dc.contributor.authorChen, H-
dc.identifier.citationIEEE Journal of Solid-State Circuits, 39(11), 2032 - 2040, Nov 2004en_US
dc.descriptionCopyright @ 2004 IEEEen_US
dc.description.abstractThis paper proposes a VLSI architecture of JPEG2000 encoder, which functionally consists of two parts: discrete wavelet transform (DWT) and embedded block coding with optimized truncation (EBCOT). For DWT, a spatial combinative lifting algorithm (SCLA)-based scheme with both 5/3 reversible and 9/7 irreversible filters is adopted to reduce 50% and 42% multiplication computations, respectively, compared with the conventional lifting-based implementation (LBI). For EBCOT, a dynamic memory control (DMC) strategy of Tier-1 encoding is adopted to reduce 60% scale of the on-chip wavelet coefficient storage and a subband parallel-processing method is employed to speed up the EBCOT context formation (CF) process; an architecture of Tier-2 encoding is presented to reduce the scale of on-chip bitstream buffering from full-tile size down to three-code-block size and considerably eliminate the iterations of the rate-distortion (RD) truncation.en_US
dc.description.sponsorshipThis work was supported in part by the China National High Technologies Research Program (863) under Grant 2002AA1Z1420en_US
dc.subjectImage Compressionen_US
dc.titleA VLSI architecture of JPEG2000 encoderen_US
pubs.organisational-data/Brunel/Brunel (Active)-
pubs.organisational-data/Brunel/Brunel (Active)/School of Engineering & Design-
Appears in Collections:Electronic and Computer Engineering
Computer Science
Dept of Computer Science Research Papers
Dept of Electronic and Computer Engineering Research Papers

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