Please use this identifier to cite or link to this item:
|Title:||On evolution of relatively large combinational logic circuits|
|Citation:||Proceeding of the NASA/DoD Workshop on Evolvable Hardware (EH'2005). Washington, DC, USA, 29 June-1 July 2005. pp. 59 - 66|
|Abstract:||Evolvable hardware (EHW) (Yao and Higuchi, 1999) is a technique introduced to automatically design circuits where the circuit configuration is carried out by evolutionary algorithms. One of the main difficulties in using EHW to solve real-world problems is the scalability. Until now, several strategies have been proposed to avoid this problem, but none of them completely tackle the issue. In this paper three different methods for evolving the most complex circuits have been tested for their scalability. These methods are bi-directional incremental evolution (SO-BIE); generalised disjunction decomposition (GD-BIE) and evolutionary strategies (ES) with dynamic mutation rate. In order to achieve the generalised conclusions the chosen approaches were tested using multipliers, traditionally used in EHW, but also logic circuits taken from MCNC (Yang, 1991) benchmark library and randomly generated circuits. The analysis of the approaches demonstrated that PLA-based ES is capable of evolving logic circuits of up to 12 inputs. The use of SO-BIE allows the generation of fully functional circuits of 14 inputs and GD-BIE is estimated to be able to evolve circuits of 21 inputs.|
|Appears in Collections:||Electronic and Computer Engineering|
Dept of Electronic and Computer Engineering Research Papers
Items in BURA are protected by copyright, with all rights reserved, unless otherwise indicated.