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Title: Novel sparse OBC based distributed arithmetic architecture for matrix transforms
Authors: Chandrasekaran, S
Amira, A
Issue Date: 2007
Publisher: IEEE
Citation: Proceedings of the IEEE Symposium on Circuits and Systems ISCAS 2007, New Orleans, USA, 27-30 May. pp. 3207 - 3210
Abstract: Inner product (IP) forms the basis of a number of signal processing algorithms and applications such as transforms, filters, communication systems etc. Distributed arithmetic (DA) provides an effective methodology to implement IP of vectors and matrices using a simple combination of memory elements, adders and shifters instead of lumped multipliers. This bit level rearrangement results in much higher computational efficiencies and yields compact designs highly suited for high performance resource constrained applications. Offset binary coding (OBC) is an effective technique to further optimize the DA, and allows us to reduce the memory requirements by a factor of two, with minimum additional computational complexity. This makes OBC-DA attractive for applications that are both resource and memory constrained. In addition, sparse matrix factorization techniques can be exploited to further reduce the size of the DA-ROMs. In this paper, the design and implementation of a novel OBC based DA is demonstrated using a generic architecture for implementing discrete orthogonal transforms (DOTs). Implementation is performed on the Xilinx Virtex-II Pro field programmable gate array (FPGA), and a detailed comparison between conventional and OBC based DA is presented to highlight the trade offs in various design metrics including performance, area and power.
ISBN: 1-4244-0921-7
Appears in Collections:Electronic and Computer Engineering
Dept of Electronic and Computer Engineering Research Papers

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