Please use this identifier to cite or link to this item: http://buratest.brunel.ac.uk/handle/2438/1764
Full metadata record
DC FieldValueLanguage
dc.contributor.authorWalton, AJ-
dc.contributor.authorStevenson, JTM-
dc.contributor.authorFallon, M-
dc.contributor.authorEvans, PSA-
dc.contributor.authorRamsey, BJ-
dc.contributor.authorHarrison, DJ-
dc.coverage.spatial6en
dc.date.accessioned2008-02-29T16:19:10Z-
dc.date.available2008-02-29T16:19:10Z-
dc.date.issued1998-
dc.identifier.citationIEEE International conf. on microelectronic test structures, 23rd - 26th March 1998, Kanazawa, Japan.en
dc.identifier.isbn0-7803-4348-4-
dc.identifier.urihttp://bura.brunel.ac.uk/handle/2438/1764-
dc.description.abstractThis paper reports on the use of microelectronic test structures to characterise a novel fabrication technique for thin-film electronic circuit boards. In this technology, circuit tracks are formed on paper-like substrates by depositing films of a metal-loaded ink via a standard lithographic printing process. Sheet resistance and line width are electrically evaluated and these quantities are compared with optical and surface profiling measurements.en
dc.format.extent762590 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoen-
dc.publisherIEEEen
dc.subjectElectric resistance measurementen
dc.subjectIntegrated circuit testing-
dc.subjectIntegrated circuit yield-
dc.subjectLithography-
dc.subjectSize measurement-
dc.titleTest structures to characterise a novel circuit fabrication technique that uses offset lithographyen
dc.typeConference Paperen
dc.identifier.doihttp://dx.doi.org/10.1109/ICMTS.1998.688032-
Appears in Collections:Design
Dept of Design Research Papers



Items in BURA are protected by copyright, with all rights reserved, unless otherwise indicated.