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dc.contributor.authorWalton, AJ-
dc.contributor.authorStevenson, JTM-
dc.contributor.authorFallon, M-
dc.contributor.authorEvans, PSA-
dc.contributor.authorRamsey, BJ-
dc.contributor.authorHarrison, DJ-
dc.identifier.citationIEEE International conf. on microelectronic test structures, 23rd - 26th March 1998, Kanazawa, Japan.en
dc.description.abstractThis paper reports on the use of microelectronic test structures to characterise a novel fabrication technique for thin-film electronic circuit boards. In this technology, circuit tracks are formed on paper-like substrates by depositing films of a metal-loaded ink via a standard lithographic printing process. Sheet resistance and line width are electrically evaluated and these quantities are compared with optical and surface profiling measurements.en
dc.format.extent762590 bytes-
dc.subjectElectric resistance measurementen
dc.subjectIntegrated circuit testing-
dc.subjectIntegrated circuit yield-
dc.subjectSize measurement-
dc.titleTest structures to characterise a novel circuit fabrication technique that uses offset lithographyen
dc.typeConference Paperen
Appears in Collections:Design
Dept of Design Research Papers

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