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|Title:||Parallel algorithms for testing finite state machines:Generating UIO sequences|
|Keywords:||Software engineering/software/program verification;software engineering/testing and debugging;Software engineering/test design;Finite State Machine;Unique Input Output Sequence generation;General Purpose Graphics Processing Units|
|Publisher:||Institute of Electrical and Electronics Engineers (IEEE)|
|Citation:||IEEE Transactions on Software Engineering, (2016)|
|Abstract:||This paper describes an efficient parallel algorithm that uses many-core GPUs for automatically deriving Unique Input Output sequences (UIOs) from Finite State Machines. The proposed algorithm uses the global scope of the GPU's global memory through coalesced memory access and minimises the transfer between CPU and GPU memory. The results of experiments indicate that the proposed method yields considerably better results compared to a single core UIO construction algorithm. Our algorithm is scalable and when multiple GPUs are added into the system the approach can handle FSMs whose size is larger than the memory available on a single GPU.|
|Appears in Collections:||Dept of Computer Science Research Papers|
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