Please use this identifier to cite or link to this item: http://buratest.brunel.ac.uk/handle/2438/2575
Title: A novel genetic algorithm for evolvable hardware
Authors: Stomeo, E
Kalganova, T
Lambert, C
Issue Date: 2006
Publisher: IEEE
Citation: IEEE Congress on Evolutionary Computation, CEC’2006. Vancouver, Canada, July, 2006. pp. 134 - 14
Abstract: Evolutionary algorithms are used for solving search and optimization problems. A new field in which they are also applied is evolvable hardware, which refers to a self-configurable electronic system. However, evolvable hardware is not widely recognized as a tool for solving real-world applications, because of the scalability problem, which limits the size of the system that may be evolved. In this paper a new genetic algorithm, particularly designed for evolving logic circuits, is presented and tested for its scalability. The proposed algorithm designs and optimizes logic circuits based on a Programmable Logic Array (PLA) structure. Furthermore it allows the evolution of large logic circuits, without the use of any decomposition techniques. The experimental results, based on the evolution of several logic circuits taken from three different benchmarks, prove that the proposed algorithm is very fast, as only a few generations are required to fully evolve the logic circuits. In addition it optimizes the evolved circuits better than the optimization offered by other evolutionary algorithms based on a PLA and FPGA structures.
URI: http://bura.brunel.ac.uk/handle/2438/2575
DOI: http://dx.doi.org/10.1109/CEC.2006.1688300
ISBN: 0-7803-9487-9
Appears in Collections:Electronic and Computer Engineering
Dept of Electronic and Computer Engineering Research Papers

Files in This Item:
File Description SizeFormat 
stomeo_CEC2006.pdf419.13 kBAdobe PDFView/Open


Items in BURA are protected by copyright, with all rights reserved, unless otherwise indicated.