Please use this identifier to cite or link to this item: http://buratest.brunel.ac.uk/handle/2438/12330
Title: Multiple-valued combinational circuits synthesized using evolvable hardware approach
Authors: Kalganova, T
Miller, J
Lipnitskaya, N
Keywords: MV;Evolvable hardware;Logic design;Combinational MV circuits
Issue Date: 1998
Publisher: Citeseer
Citation: The 7th Workshop on Post-Binary Ultra Large Scale Integration Systems (ULSI’98) in association with ISMVL, pp. 27 - 29, 1998
Abstract: In this paper a gate-level evolvable hardware technique for designing multiple-valued (MV) circuits, which is easily adapted for the different types of MV gates associated with operations corresponding to different algebra types and can include other more complex logical expressions (e.g.T-gate) is proposed. The technique is based on evolving the functionality and connectivity of a rectangular array of logic cells. The evolved 3-valued 1- digit adder with carry circuit is examined as an example. The issue of choosing the optimal set of MV gates used to evolve circuit is also discussed.
URI: http://bura.brunel.ac.uk/handle/2438/12330
Appears in Collections:Dept of Electronic and Computer Engineering Research Papers

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